Tutorial 6 tasks and submission

Problems 4 & 6 have not been covered in lectures yet so it is OK to only attempt 1,2,3 and 5

1. What happens to the gate delay if the threshold voltage is raised by 100 mV (absolute value) for both NMOS and PMOS transistors in a CMOS circuit? Hint, investigate the current in saturation for a fixed gate bias V_GS=const condition.
   
   
2. Explain how channel width is defined in FinFET technology and how larger widths can be achieved for PMOS devices in balanced CMOS inverters.
3. An close to ideal MOSFET has (inverse) subthreshold swing of S = 60 mV/decade of current meaning that the offstate current I_off changes a factor ox x10 (note was x100 in an earlier typo)  for each incremental change in V_GS of 60 mV at T= 300 K.  
   1. How much does the current change for S = [70 , 80 or 90 mV/dec]?
   2. How much does S become if it is originally 60 mV/dec and the operational temperature is lowered to T = 77 K (liquid Nitrogen)? How does that influence I_off, give a numerical example along with a graph showing both T = 300 K and T = 77 K subthreshold IV!
4. Explain the complete cell design for an imaging pixel that is color sensitive. Draw a cross-section of the pixel. (NOTE not covered in lectures yet)
5. A typical modern MOSFET has a saturation current of about 1000 μA/μm  (current normalized to gate width W). A chip built in CMOS technology  dissipates about 200 W of dynamic power. Assume that W = 200 nm and that the supply voltage is very low, pick a value from the lecture material. How many transistors would this chip contain?
6. Both CMOS logic circuits and the three main memory types are charge-based. Explain what this means for each case. What is the connection between the stored charge and the memory and logic states/levels that are sensed as voltages? (NOTE not covered in lectures yet)