What happens to the gate delay if the threshold voltage is raised by 100 mV (absolute value) for both NMOS and PMOS transistors in a CMOS circuit?
Explain how channel width is defined in FinFET technology and how larger widths can be achieved for PMOS devices in balanced CMOS inverters.
Explain the complete cell design for an imaging pixel that is color sensitive. Draw a cross-section of the pixel.
Both CMOS logic circuits and the three main memory types are charge-based. Explain what this means for each case. What is the connection between the stored charge and the memory and logic states/levels that are sensed as voltages?
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